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Additional resources for ACM-SIGDA Physical Design Workshop #5 1996: Proceedings
Dt)- rO 5(CL + Co :+ Unconstrained Wire-Sizing ire J-21 10 ro(CL + co fag f(t)dt) co(Rd + rO jo+ 7 dt) ym-n gives minimum delay. f f (t)dt) co(Rd + rO 1X f(tdt) ro(CL + CO - Since f is an optimal wire-sizing function, we have Ymi. f(x) and hence 03 RJ f 2 (X) Figure 3: Local modification of an optimal wire-sizing function. Theorem 1 Let f be an optimal wire-sizing function. We have f 2 (X) = ro(CL + co Jf: f(t)dt) co(Rd + ro fj, (tdt) ro(CL + co fJ f(t)dt) co(Rd + ro CL fo I(t)dt) For the case where f is not continuous at x, we have f is either left-continuous or right-continuous at x.
Lin of UCSB for providing us his greedy channel router implementation. 33 SIMULTANEOUS TRANSISTOR AND INTERCONNECT SIZING USING GENERAL DOMINANCE PROPERTY Jason Cong and Lei He Department of Computer Science University of California, Los Angeles, CA 90095 * given cell library for performance optimization. Recent gate sizing works can be found in [1, 2, 3]. However, all these works ignored the sizing of interconnects. The interconnect sizing problem, often called the wiresizing problem, was first introduced in [6, 7] where the authors developed the first polynomial-time optimal wiresizing algorithm to minimize the weighted Elmore delay between the unique source and a set of critical sinks.
35 Experimental Results and Concluding Remarks a E V I We implemented and tested our algorithm in C on a Sun Sparc 5 workstation with 16 MB memory. The parameters used are shown in Table 3. The results are given in Table 4. The first column labeled "Precision Requirement" specifies the required accuracy of the wire width values. The second column shows the number of Newton-Raphson iterations. Our results show that even under very strict precision requirement the number of iterations is at most 7.
ACM-SIGDA Physical Design Workshop #5 1996: Proceedings by ACM-SIGDA